344 lines
11 KiB
C
344 lines
11 KiB
C
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// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp32-hal-i2c.h"
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#include "esp32-hal.h"
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#if !CONFIG_DISABLE_HAL_LOCKS
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#endif
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#include "esp_attr.h"
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#include "esp_system.h"
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#include "soc/soc_caps.h"
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#include "soc/i2c_periph.h"
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#include "hal/i2c_hal.h"
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#include "hal/i2c_ll.h"
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#include "driver/i2c.h"
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typedef volatile struct {
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bool initialized;
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uint32_t frequency;
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#if !CONFIG_DISABLE_HAL_LOCKS
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SemaphoreHandle_t lock;
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#endif
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} i2c_bus_t;
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static i2c_bus_t bus[SOC_I2C_NUM];
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bool i2cIsInit(uint8_t i2c_num){
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if(i2c_num >= SOC_I2C_NUM){
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return false;
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}
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return bus[i2c_num].initialized;
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}
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esp_err_t i2cInit(uint8_t i2c_num, int8_t sda, int8_t scl, uint32_t frequency){
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if(i2c_num >= SOC_I2C_NUM){
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return ESP_ERR_INVALID_ARG;
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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if(bus[i2c_num].lock == NULL){
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bus[i2c_num].lock = xSemaphoreCreateMutex();
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if(bus[i2c_num].lock == NULL){
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log_e("xSemaphoreCreateMutex failed");
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return ESP_ERR_NO_MEM;
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}
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}
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//acquire lock
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if(xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE){
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log_e("could not acquire lock");
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return ESP_FAIL;
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}
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#endif
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if(bus[i2c_num].initialized){
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log_e("bus is already initialized");
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return ESP_FAIL;
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}
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if(!frequency){
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frequency = 100000UL;
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} else if(frequency > 1000000UL){
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frequency = 1000000UL;
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}
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log_i("Initialising I2C Master: sda=%d scl=%d freq=%d", sda, scl, frequency);
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i2c_config_t conf = { };
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conf.mode = I2C_MODE_MASTER;
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conf.scl_io_num = (gpio_num_t)scl;
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conf.sda_io_num = (gpio_num_t)sda;
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conf.scl_pullup_en = GPIO_PULLUP_ENABLE;
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conf.sda_pullup_en = GPIO_PULLUP_ENABLE;
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conf.master.clk_speed = frequency;
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conf.clk_flags = I2C_SCLK_SRC_FLAG_FOR_NOMAL; //Any one clock source that is available for the specified frequency may be choosen
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esp_err_t ret = i2c_param_config((i2c_port_t)i2c_num, &conf);
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if (ret != ESP_OK) {
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log_e("i2c_param_config failed");
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} else {
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ret = i2c_driver_install((i2c_port_t)i2c_num, conf.mode, 0, 0, 0);
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if (ret != ESP_OK) {
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log_e("i2c_driver_install failed");
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} else {
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bus[i2c_num].initialized = true;
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bus[i2c_num].frequency = frequency;
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//Clock Stretching Timeout: 20b:esp32, 5b:esp32-c3, 24b:esp32-s2
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i2c_set_timeout((i2c_port_t)i2c_num, I2C_LL_MAX_TIMEOUT);
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}
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//release lock
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xSemaphoreGive(bus[i2c_num].lock);
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#endif
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return ret;
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}
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esp_err_t i2cDeinit(uint8_t i2c_num){
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esp_err_t err = ESP_FAIL;
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if(i2c_num >= SOC_I2C_NUM){
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return ESP_ERR_INVALID_ARG;
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//acquire lock
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if(bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE){
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log_e("could not acquire lock");
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return err;
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}
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#endif
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if(!bus[i2c_num].initialized){
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log_e("bus is not initialized");
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} else {
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err = i2c_driver_delete((i2c_port_t)i2c_num);
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if(err == ESP_OK){
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bus[i2c_num].initialized = false;
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}
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//release lock
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xSemaphoreGive(bus[i2c_num].lock);
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#endif
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return err;
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}
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esp_err_t i2cWrite(uint8_t i2c_num, uint16_t address, const uint8_t* buff, size_t size, uint32_t timeOutMillis){
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esp_err_t ret = ESP_FAIL;
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i2c_cmd_handle_t cmd = NULL;
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if(i2c_num >= SOC_I2C_NUM){
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return ESP_ERR_INVALID_ARG;
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//acquire lock
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if(bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE){
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log_e("could not acquire lock");
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return ret;
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}
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#endif
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if(!bus[i2c_num].initialized){
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log_e("bus is not initialized");
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goto end;
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}
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//short implementation does not support zero size writes (example when scanning) PR in IDF?
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//ret = i2c_master_write_to_device((i2c_port_t)i2c_num, address, buff, size, timeOutMillis / portTICK_RATE_MS);
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ret = ESP_OK;
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uint8_t cmd_buff[I2C_LINK_RECOMMENDED_SIZE(1)] = { 0 };
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cmd = i2c_cmd_link_create_static(cmd_buff, I2C_LINK_RECOMMENDED_SIZE(1));
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ret = i2c_master_start(cmd);
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if (ret != ESP_OK) {
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goto end;
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}
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ret = i2c_master_write_byte(cmd, (address << 1) | I2C_MASTER_WRITE, true);
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if (ret != ESP_OK) {
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goto end;
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}
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if(size){
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ret = i2c_master_write(cmd, buff, size, true);
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if (ret != ESP_OK) {
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goto end;
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}
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}
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ret = i2c_master_stop(cmd);
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if (ret != ESP_OK) {
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goto end;
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}
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ret = i2c_master_cmd_begin((i2c_port_t)i2c_num, cmd, timeOutMillis / portTICK_RATE_MS);
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end:
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if(cmd != NULL){
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i2c_cmd_link_delete_static(cmd);
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//release lock
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xSemaphoreGive(bus[i2c_num].lock);
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#endif
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return ret;
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}
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esp_err_t i2cRead(uint8_t i2c_num, uint16_t address, uint8_t* buff, size_t size, uint32_t timeOutMillis, size_t *readCount){
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esp_err_t ret = ESP_FAIL;
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if(i2c_num >= SOC_I2C_NUM){
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return ESP_ERR_INVALID_ARG;
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//acquire lock
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if(bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE){
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log_e("could not acquire lock");
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return ret;
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}
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#endif
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if(!bus[i2c_num].initialized){
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log_e("bus is not initialized");
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} else {
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ret = i2c_master_read_from_device((i2c_port_t)i2c_num, address, buff, size, timeOutMillis / portTICK_RATE_MS);
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if(ret == ESP_OK){
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*readCount = size;
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} else {
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*readCount = 0;
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}
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//release lock
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xSemaphoreGive(bus[i2c_num].lock);
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#endif
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return ret;
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}
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esp_err_t i2cWriteReadNonStop(uint8_t i2c_num, uint16_t address, const uint8_t* wbuff, size_t wsize, uint8_t* rbuff, size_t rsize, uint32_t timeOutMillis, size_t *readCount){
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esp_err_t ret = ESP_FAIL;
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if(i2c_num >= SOC_I2C_NUM){
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return ESP_ERR_INVALID_ARG;
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//acquire lock
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if(bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE){
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log_e("could not acquire lock");
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return ret;
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}
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#endif
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if(!bus[i2c_num].initialized){
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log_e("bus is not initialized");
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} else {
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ret = i2c_master_write_read_device((i2c_port_t)i2c_num, address, wbuff, wsize, rbuff, rsize, timeOutMillis / portTICK_RATE_MS);
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if(ret == ESP_OK){
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*readCount = rsize;
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} else {
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*readCount = 0;
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}
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//release lock
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xSemaphoreGive(bus[i2c_num].lock);
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#endif
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return ret;
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}
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esp_err_t i2cSetClock(uint8_t i2c_num, uint32_t frequency){
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esp_err_t ret = ESP_FAIL;
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if(i2c_num >= SOC_I2C_NUM){
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return ESP_ERR_INVALID_ARG;
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}
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#if !CONFIG_DISABLE_HAL_LOCKS
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//acquire lock
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if(bus[i2c_num].lock == NULL || xSemaphoreTake(bus[i2c_num].lock, portMAX_DELAY) != pdTRUE){
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log_e("could not acquire lock");
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return ret;
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}
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#endif
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if(!bus[i2c_num].initialized){
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log_e("bus is not initialized");
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goto end;
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}
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if(bus[i2c_num].frequency == frequency){
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ret = ESP_OK;
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goto end;
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}
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if(!frequency){
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frequency = 100000UL;
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} else if(frequency > 1000000UL){
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frequency = 1000000UL;
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}
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// Freq limitation when using different clock sources
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#define I2C_CLK_LIMIT_REF_TICK (1 * 1000 * 1000 / 20) /*!< Limited by REF_TICK, no more than REF_TICK/20*/
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#define I2C_CLK_LIMIT_APB (80 * 1000 * 1000 / 20) /*!< Limited by APB, no more than APB/20*/
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#define I2C_CLK_LIMIT_RTC (20 * 1000 * 1000 / 20) /*!< Limited by RTC, no more than RTC/20*/
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#define I2C_CLK_LIMIT_XTAL (40 * 1000 * 1000 / 20) /*!< Limited by RTC, no more than XTAL/20*/
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typedef struct {
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uint8_t character; /*!< I2C source clock characteristic */
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uint32_t clk_freq; /*!< I2C source clock frequency */
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} i2c_clk_alloc_t;
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// i2c clock characteristic, The order is the same as i2c_sclk_t.
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static i2c_clk_alloc_t i2c_clk_alloc[I2C_SCLK_MAX] = {
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{0, 0},
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#if SOC_I2C_SUPPORT_APB
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{0, I2C_CLK_LIMIT_APB}, /*!< I2C APB clock characteristic*/
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#endif
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#if SOC_I2C_SUPPORT_XTAL
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{0, I2C_CLK_LIMIT_XTAL}, /*!< I2C XTAL characteristic*/
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#endif
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#if SOC_I2C_SUPPORT_RTC
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{I2C_SCLK_SRC_FLAG_LIGHT_SLEEP | I2C_SCLK_SRC_FLAG_AWARE_DFS, I2C_CLK_LIMIT_RTC}, /*!< I2C 20M RTC characteristic*/
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#endif
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#if SOC_I2C_SUPPORT_REF_TICK
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{I2C_SCLK_SRC_FLAG_AWARE_DFS, I2C_CLK_LIMIT_REF_TICK}, /*!< I2C REF_TICK characteristic*/
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#endif
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};
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i2c_sclk_t src_clk = I2C_SCLK_DEFAULT;
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ret = ESP_OK;
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for (i2c_sclk_t clk = I2C_SCLK_DEFAULT + 1; clk < I2C_SCLK_MAX; clk++) {
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#if CONFIG_IDF_TARGET_ESP32S3
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if (clk == I2C_SCLK_RTC) { // RTC clock for s3 is unaccessable now.
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continue;
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}
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#endif
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if (frequency <= i2c_clk_alloc[clk].clk_freq) {
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src_clk = clk;
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break;
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}
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}
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if(src_clk == I2C_SCLK_MAX){
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log_e("clock source could not be selected");
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ret = ESP_FAIL;
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} else {
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i2c_hal_context_t hal;
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hal.dev = I2C_LL_GET_HW(i2c_num);
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i2c_hal_set_bus_timing(&(hal), frequency, src_clk);
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bus[i2c_num].frequency = frequency;
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//Clock Stretching Timeout: 20b:esp32, 5b:esp32-c3, 24b:esp32-s2
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i2c_set_timeout((i2c_port_t)i2c_num, I2C_LL_MAX_TIMEOUT);
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}
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end:
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#if !CONFIG_DISABLE_HAL_LOCKS
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//release lock
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xSemaphoreGive(bus[i2c_num].lock);
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#endif
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return ret;
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}
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esp_err_t i2cGetClock(uint8_t i2c_num, uint32_t * frequency){
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if(i2c_num >= SOC_I2C_NUM){
|
||
|
|
return ESP_ERR_INVALID_ARG;
|
||
|
|
}
|
||
|
|
if(!bus[i2c_num].initialized){
|
||
|
|
log_e("bus is not initialized");
|
||
|
|
return ESP_FAIL;
|
||
|
|
}
|
||
|
|
*frequency = bus[i2c_num].frequency;
|
||
|
|
return ESP_OK;
|
||
|
|
}
|